Static Timing Analysis

Project : UART_RxTx01
Build Time : 03/25/18 16:30:32
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.50
VDDABUF : 5.50
VDDD : 5.50
VDDIO0 : 5.50
VDDIO1 : 5.50
VDDIO2 : 5.50
VDDIO3 : 5.50
VUSB : 5.50
Voltage : 5.5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 56.660 MHz
Clock_1 CyMASTER_CLK 461.538 kHz 461.538 kHz 49.249 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 2166.67ns(461.538 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 49.249 MHz 20.305 2146.362
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,5) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 8.014
macrocell6 U(3,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.331
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 51.530 MHz 19.406 2147.261
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,4) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 7.115
macrocell6 U(3,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.331
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 53.336 MHz 18.749 2147.918
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,5) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_bitclk_enable_pre\/main_2 4.467
macrocell3 U(2,3) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_2 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.672
datapathcell1 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 53.342 MHz 18.747 2147.920
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,5) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_bitclk_enable_pre\/main_1 4.465
macrocell3 U(2,3) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_1 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.672
datapathcell1 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2 \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 53.622 MHz 18.649 2148.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2 1.940
Route 1 \UART_1:BUART:txbitcount_2\ \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_2 \UART_1:BUART:tx_bitclk_enable_pre\/main_3 3.677
macrocell3 U(2,3) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_3 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.672
datapathcell1 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0 \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 53.625 MHz 18.648 2148.019
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0 1.940
Route 1 \UART_1:BUART:txbitcount_0\ \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_0 \UART_1:BUART:tx_bitclk_enable_pre\/main_5 3.676
macrocell3 U(2,3) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_5 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.672
datapathcell1 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1 \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 53.628 MHz 18.647 2148.020
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/clock \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1 1.940
Route 1 \UART_1:BUART:txbitcount_1\ \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/count_1 \UART_1:BUART:tx_bitclk_enable_pre\/main_4 3.675
macrocell3 U(2,3) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_4 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.672
datapathcell1 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load 56.680 MHz 17.643 2149.024
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,3) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load\/main_0 5.367
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load\ \UART_1:BUART:counter_load\/main_0 \UART_1:BUART:counter_load\/q 3.350
Route 1 \UART_1:BUART:counter_load\ \UART_1:BUART:counter_load\/q \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load 2.316
count7cell U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load 57.584 MHz 17.366 2149.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,3) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load\/main_3 5.090
macrocell2 U(2,5) 1 \UART_1:BUART:counter_load\ \UART_1:BUART:counter_load\/main_3 \UART_1:BUART:counter_load\/q 3.350
Route 1 \UART_1:BUART:counter_load\ \UART_1:BUART:counter_load\/q \UART_1:BUART:sTX:sCLOCK:TxBitCounter\/load 2.316
count7cell U(2,5) 1 \UART_1:BUART:sTX:sCLOCK:TxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 59.126 MHz 16.913 2149.754
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(2,3) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_bitclk_enable_pre\/main_0 2.631
macrocell3 U(2,3) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.672
datapathcell1 U(2,5) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
RX(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 56.660 MHz 17.649 24.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.490
macrocell7 U(3,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell2 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:pollcount_0\/main_2 83.126 MHz 12.030 29.637
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.490
macrocell24 U(3,5) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:rx_state_2\/main_8 83.935 MHz 11.914 29.753
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_state_2\/main_8 6.374
macrocell20 U(3,3) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:rx_last\/main_0 83.935 MHz 11.914 29.753
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_last\/main_0 6.374
macrocell26 U(3,3) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:rx_state_0\/main_9 89.582 MHz 11.163 30.504
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.623
macrocell17 U(3,4) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:rx_status_3\/main_6 89.582 MHz 11.163 30.504
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.623
macrocell25 U(3,4) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:pollcount_1\/main_3 89.912 MHz 11.122 30.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.582
macrocell23 U(3,4) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 1.566
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(2,3) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.316
statusicell3 U(3,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(3,4) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.896
statusicell2 U(2,3) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 2.148
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(3,4) 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/clock_0 \PWM_1:PWMUDB:status_1\/q 1.250
Route 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 2.898
statusicell3 U(3,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_0\/main_5 2.926
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_0\/main_5 2.306
macrocell17 U(3,4) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.926
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.306
macrocell18 U(3,4) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.312
macrocell21 U(3,4) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_1\/main_0 2.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:pollcount_1\/main_0 2.312
macrocell23 U(3,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.314
macrocell21 U(3,4) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_1\/main_1 2.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:pollcount_1\/main_1 2.314
macrocell23 U(3,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART_1:BUART:rx_count_0\ \UART_1:BUART:sRX:RxBitCounter\/count_0 \UART_1:BUART:rx_bitclk_enable\/main_2 2.326
macrocell21 U(3,4) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
RX(0)/fb \UART_1:BUART:pollcount_1\/main_3 7.612
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.582
macrocell23 U(3,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.653
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.623
macrocell17 U(3,4) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:rx_status_3\/main_6 7.653
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.623
macrocell25 U(3,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:rx_state_2\/main_8 8.404
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_state_2\/main_8 6.374
macrocell20 U(3,3) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:rx_last\/main_0 8.404
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_last\/main_0 6.374
macrocell26 U(3,3) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:pollcount_0\/main_2 8.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.490
macrocell24 U(3,5) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 14.179
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[1] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.030
Route 1 Net_45 RX(0)/fb \UART_1:BUART:rx_postpoll\/main_1 6.490
macrocell7 U(3,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell2 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock_1
Source Destination Delay (ns)
CTS(0)_PAD \UART_1:BUART:tx_state_0\/main_5 17.323
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 CTS(0)_PAD CTS(0)_PAD CTS(0)/pad_in 0.000
iocell4 P6[0] 1 CTS(0) CTS(0)/pad_in CTS(0)/fb 7.816
Route 1 Net_3631 CTS(0)/fb \UART_1:BUART:tx_state_0\/main_5 5.997
macrocell13 U(2,5) 1 \UART_1:BUART:tx_state_0\ SETUP 3.510
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
\UART_1:BUART:txn\/q TX(0)_PAD 28.920
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(2,5) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_66/main_0 2.602
macrocell1 U(3,5) 1 Net_66 Net_66/main_0 Net_66/q 3.350
Route 1 Net_66 Net_66/q TX(0)/pin_input 6.467
iocell2 P0[0] 1 TX(0) TX(0)/pin_input TX(0)/pad_out 15.251
Route 1 TX(0)_PAD TX(0)/pad_out TX(0)_PAD 0.000
Clock Clock path delay 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb RTS(0)_PAD 26.483
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 Net_3632 \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb RTS(0)/pin_input 7.177
iocell3 P6[6] 1 RTS(0) RTS(0)/pin_input RTS(0)/pad_out 15.726
Route 1 RTS(0)_PAD RTS(0)/pad_out RTS(0)_PAD 0.000
Clock Clock path delay 0.000
Net_3983/q P6_2(0)_PAD 24.475
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(2,4) 1 Net_3983 Net_3983/clock_0 Net_3983/q 1.250
Route 1 Net_3983 Net_3983/q P6_2(0)/pin_input 7.479
iocell5 P6[2] 1 P6_2(0) P6_2(0)/pin_input P6_2(0)/pad_out 15.746
Route 1 P6_2(0)_PAD P6_2(0)/pad_out P6_2(0)_PAD 0.000
Clock Clock path delay 0.000