Static Timing Analysis

Project : UART_RxTx01
Build Time : 06/10/18 20:47:03
Device : CY8C4248BZI-L489
Temperature : -40C - 85C
VBUS : 5.00
VDDA_0 : 5.50
VDDA_1 : 5.50
VDDA_CTB : 5.50
VDDD : 5.50
VDDIO : 3.30
VDDIO_0 : 5.50
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_3 : 3.30
VDDIO_4 : 3.30
VDDIO_A : 5.50
VDDIO_A_1 : 5.50
Voltage : 5.5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyHFCLK 77.922 kHz 77.922 kHz 55.157 MHz
UART_1_SCBCLK CyHFCLK 1.412 MHz 1.412 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
UART_1_SCBCLK(FFB) UART_1_SCBCLK(FFB) 1.412 MHz 1.412 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 12833.3ns(77.9221 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 55.157 MHz 18.130 12815.203
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.760
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 63.898 MHz 15.650 12817.683
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.880
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 72.192 MHz 13.852 12819.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 2.779
macrocell2 U(1,3) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.303
statusicell1 U(1,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 83.465 MHz 11.981 12821.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.791
macrocell4 U(1,3) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 83.465 MHz 11.981 12821.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.791
macrocell6 U(1,3) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 83.465 MHz 11.981 12821.352
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 2.791
macrocell8 U(1,3) 1 Net_5269 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 88.121 MHz 11.348 12821.985
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 2.875
macrocell2 U(1,3) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.303
statusicell1 U(1,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 118.694 MHz 8.425 12824.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 2.580
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.335
macrocell3 U(1,3) 1 \PWM_1:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 130.959 MHz 7.636 12825.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 2.876
macrocell8 U(1,3) 1 Net_5269 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 141.523 MHz 7.066 12826.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,3) 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/clock_0 \PWM_1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 2.306
macrocell7 U(1,3) 1 \PWM_1:PWMUDB:status_1\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 1.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(1,3) 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/clock_0 \PWM_1:PWMUDB:status_1\/q 1.250
Route 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 2.313
statusicell1 U(1,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 1.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,3) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.324
statusicell1 U(1,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,3) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.294
macrocell6 U(1,3) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,3) 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/clock_0 \PWM_1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 2.306
macrocell7 U(1,3) 1 \PWM_1:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 4.126
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 2.876
macrocell8 U(1,3) 1 Net_5269 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 4.130
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.880
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 4.375
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.335
macrocell3 U(1,3) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 5.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.791
macrocell4 U(1,3) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 5.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.791
macrocell6 U(1,3) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 5.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 2.791
macrocell8 U(1,3) 1 Net_5269 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_5269/q P5_4(0)_PAD 26.215
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,3) 1 Net_5269 Net_5269/clock_0 Net_5269/q 1.250
Route 1 Net_5269 Net_5269/q Net_3983/main_1 2.310
macrocell1 U(1,3) 1 Net_3983 Net_3983/main_1 Net_3983/q 3.350
Route 1 Net_3983 Net_3983/q P5_4(0)/pin_input 5.455
iocell2 P5[4] 1 P5_4(0) P5_4(0)/pin_input P5_4(0)/pad_out 13.850
Route 1 P5_4(0)_PAD P5_4(0)/pad_out P5_4(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyHFCLK
Source Destination Delay (ns)
\Control_Reg_1:Sync:ctrl_reg\/control_0 P5_4(0)_PAD 27.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_5057 \Control_Reg_1:Sync:ctrl_reg\/control_0 Net_3983/main_0 2.332
macrocell1 U(1,3) 1 Net_3983 Net_3983/main_0 Net_3983/q 3.350
Route 1 Net_3983 Net_3983/q P5_4(0)/pin_input 5.455
iocell2 P5[4] 1 P5_4(0) P5_4(0)/pin_input P5_4(0)/pad_out 13.850
Route 1 P5_4(0)_PAD P5_4(0)/pad_out P5_4(0)_PAD 0.000
Clock Clock path delay 0.000