Static Timing Analysis

Project : UART_RxTx01
Build Time : 11/04/18 17:28:20
Device : CY8C4247AZI-M485
Temperature : -40C - 85C
VDDA_0 : 5.50
VDDA_CTB : 5.50
VDDD : 5.50
VDDD_0 : 5.50
VDDD_1 : 5.50
VDDIO : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_A : 5.50
VDDIO_A_1 : 5.50
Voltage : 5.5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyHFCLK 77.922 kHz 77.922 kHz 55.145 MHz
UART_1_SCBCLK CyHFCLK 461.538 kHz 461.538 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
UART_1_SCBCLK(FFB) UART_1_SCBCLK(FFB) 461.538 kHz 461.538 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 12833.3ns(77.9221 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 55.145 MHz 18.134 12815.199
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.764
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 63.886 MHz 15.653 12817.680
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.883
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 11.520
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 72.062 MHz 13.877 12819.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 3.850
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 2.789
macrocell1 U(0,1) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(0,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 84.810 MHz 11.791 12821.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 2.601
macrocell8 U(0,1) 1 Net_5269 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 84.875 MHz 11.782 12821.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.592
macrocell4 U(0,1) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 84.875 MHz 11.782 12821.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 5.680
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.592
macrocell6 U(0,1) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 87.958 MHz 11.369 12821.964
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 2.881
macrocell1 U(0,1) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.318
statusicell1 U(0,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 1.570
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 118.793 MHz 8.418 12824.915
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 2.580
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.328
macrocell3 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 130.993 MHz 7.634 12825.699
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 2.874
macrocell8 U(0,1) 1 Net_5269 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 141.583 MHz 7.063 12826.270
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,1) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.303
macrocell6 U(0,1) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 1.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell7 U(0,1) 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/clock_0 \PWM_1:PWMUDB:status_1\/q 1.250
Route 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 2.314
statusicell1 U(0,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 1.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(0,1) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.323
statusicell1 U(0,1) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 3.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(0,1) 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/clock_0 \PWM_1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 2.288
macrocell7 U(0,1) 1 \PWM_1:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(0,1) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.303
macrocell6 U(0,1) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 4.124
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 2.874
macrocell8 U(0,1) 1 Net_5269 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 4.133
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.883
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 4.368
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(0,1) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 2.040
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.328
macrocell3 U(0,1) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 5.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.592
macrocell4 U(0,1) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 5.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.592
macrocell6 U(0,1) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 5.731
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 3.130
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 2.601
macrocell8 U(0,1) 1 Net_5269 HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_5269/q P0_6(0)_PAD 27.835
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(0,1) 1 Net_5269 Net_5269/clock_0 Net_5269/q 1.250
Route 1 Net_5269 Net_5269/q Net_3983/main_1 2.311
macrocell2 U(1,1) 1 Net_3983 Net_3983/main_1 Net_3983/q 3.350
Route 1 Net_3983 Net_3983/q P0_6(0)/pin_input 5.444
iocell2 P0[6] 1 P0_6(0) P0_6(0)/pin_input P0_6(0)/pad_out 15.480
Route 1 P0_6(0)_PAD P0_6(0)/pad_out P0_6(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyHFCLK
Source Destination Delay (ns)
\Control_Reg_1:Sync:ctrl_reg\/control_0 P0_6(0)_PAD 29.159
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,1) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_5057 \Control_Reg_1:Sync:ctrl_reg\/control_0 Net_3983/main_0 2.305
macrocell2 U(1,1) 1 Net_3983 Net_3983/main_0 Net_3983/q 3.350
Route 1 Net_3983 Net_3983/q P0_6(0)/pin_input 5.444
iocell2 P0[6] 1 P0_6(0) P0_6(0)/pin_input P0_6(0)/pad_out 15.480
Route 1 P0_6(0)_PAD P0_6(0)/pad_out P0_6(0)_PAD 0.000
Clock Clock path delay 0.000