Static Timing Analysis

Project : UART_RxTx01
Build Time : 10/07/18 13:43:23
Device : CY8C5888AXI-LP096
Temperature : -40C - 85/125C
VDDA : 5.50
VDDABUF : 5.50
VDDD : 5.50
VDDIO0 : 5.50
VDDIO1 : 5.50
VDDIO2 : 5.50
VDDIO3 : 5.50
VUSB : 5.50
Voltage : 5.5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 61.188 MHz
UART_1_IntClock CyMASTER_CLK 307.692 kHz 307.692 kHz 50.589 MHz
Clock_1 CyMASTER_CLK 77.922 kHz 77.922 kHz 90.432 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 12833.3ns(77.9221 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 90.432 MHz 11.058 12822.275
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 2.598
macrocell10 U(0,3) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.320
statusicell3 U(1,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 91.483 MHz 10.931 12822.402
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.581
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 99.691 MHz 10.031 12823.302
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 2.611
macrocell10 U(0,3) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.320
statusicell3 U(1,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 100.341 MHz 9.966 12823.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 3.946
macrocell28 U(0,5) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 100.341 MHz 9.966 12823.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 3.946
macrocell30 U(0,5) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 100.664 MHz 9.934 12823.399
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.624
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 120.019 MHz 8.332 12825.001
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 2.312
macrocell32 U(0,3) 1 Net_5269 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 135.667 MHz 7.371 12825.962
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 2.611
macrocell32 U(0,3) 1 Net_5269 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 141.703 MHz 7.057 12826.276
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,3) 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/clock_0 \PWM_1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 2.297
macrocell31 U(1,3) 1 \PWM_1:PWMUDB:status_1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 141.864 MHz 7.049 12826.284
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,5) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.289
macrocell30 U(0,5) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 61.188 MHz 16.343 25.324
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.001
macrocell7 U(1,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.288
datapathcell3 U(1,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 79.599 MHz 12.563 29.104
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.819
macrocell26 U(1,3) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 85.896 MHz 11.642 30.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.898
macrocell23 U(1,4) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 85.896 MHz 11.642 30.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.898
macrocell24 U(1,4) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 85.896 MHz 11.642 30.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.898
macrocell25 U(1,4) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 93.067 MHz 10.745 30.922
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.001
macrocell20 U(1,5) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 93.197 MHz 10.730 30.937
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 4.986
macrocell17 U(1,5) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 3250ns(307.692 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 50.589 MHz 19.767 3230.233
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(1,5) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 7.478
macrocell6 U(1,5) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.329
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 54.463 MHz 18.361 3231.639
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,4) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 4.658
macrocell3 U(1,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.913
datapathcell2 U(1,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:pollcount_1\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 56.831 MHz 17.596 3232.404
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,4) 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/clock_0 \UART_1:BUART:pollcount_1\/q 1.250
Route 1 \UART_1:BUART:pollcount_1\ \UART_1:BUART:pollcount_1\/q \UART_1:BUART:rx_postpoll\/main_0 7.238
macrocell7 U(1,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.288
datapathcell3 U(1,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.524 MHz 17.087 3232.913
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,3) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.384
macrocell3 U(1,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.913
datapathcell2 U(1,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.577 MHz 16.785 3233.215
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,4) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.082
macrocell3 U(1,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.913
datapathcell2 U(1,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 60.857 MHz 16.432 3233.568
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,5) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 4.143
macrocell6 U(1,5) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.329
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.763 MHz 16.191 3233.809
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 3.548
macrocell3 U(1,4) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.913
datapathcell2 U(1,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 64.309 MHz 15.550 3234.450
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,5) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 3.261
macrocell6 U(1,5) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.329
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 66.966 MHz 14.933 3235.067
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 Net_5517 \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 4.568
macrocell8 U(1,3) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 2.935
statusicell2 U(1,4) 1 \UART_1:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 67.177 MHz 14.886 3235.114
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(1,5) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 2.597
macrocell6 U(1,5) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.329
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 1.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(1,3) 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/clock_0 \PWM_1:PWMUDB:status_1\/q 1.250
Route 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 2.313
statusicell3 U(1,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.683
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,3) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.323
macrocell27 U(0,3) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.908
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(0,5) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 3.658
statusicell3 U(1,3) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 3.092
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_5269/main_1 2.312
macrocell32 U(0,3) 1 Net_5269 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,5) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.289
macrocell30 U(0,5) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(1,3) 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/clock_0 \PWM_1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 2.297
macrocell31 U(1,3) 1 \PWM_1:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 3.861
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_5269/main_0 2.611
macrocell32 U(0,3) 1 Net_5269 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.874
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(0,3) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.624
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 4.391
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 1.810
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.581
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 4.726
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,3) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 3.946
macrocell28 U(0,5) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.220
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 4.986
macrocell17 U(1,5) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 7.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.001
macrocell20 U(1,5) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 8.132
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 5.898
macrocell23 U(1,4) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 8.132
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 5.898
macrocell24 U(1,4) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 8.132
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.898
macrocell25 U(1,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 9.053
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 6.819
macrocell26 U(1,3) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 12.873
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P6[1] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.234
Route 1 Net_5416 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 5.001
macrocell7 U(1,5) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.288
datapathcell3 U(1,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 1.585
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(1,4) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.335
statusicell2 U(1,4) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 2.828
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 2.638
macrocell13 U(0,3) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 2.828
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 2.638
macrocell15 U(0,3) 1 \UART_1:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 3.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.791
macrocell18 U(1,5) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_2\/main_5 3.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_2\/main_5 2.791
macrocell20 U(1,5) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_0\/main_5 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_0\/main_5 2.793
macrocell17 U(1,5) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_3\/main_5 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_1:BUART:rx_count_6\ \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_3\/main_5 2.793
macrocell19 U(1,5) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 3.414
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 2.794
macrocell18 U(1,5) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_6 3.414
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_6 2.794
macrocell20 U(1,5) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 3.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 2.800
macrocell17 U(1,5) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ UART_1_IntClock
Source Destination Delay (ns)
CTS_1(0)_PAD \UART_1:BUART:tx_state_0\/main_6 15.658
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 CTS_1(0)_PAD CTS_1(0)_PAD CTS_1(0)/pad_in 0.000
iocell5 P15[4] 1 CTS_1(0) CTS_1(0)/pad_in CTS_1(0)/fb 7.473
Route 1 Net_5518 CTS_1(0)/fb \UART_1:BUART:tx_state_0\/main_6 4.675
macrocell13 U(0,3) 1 \UART_1:BUART:tx_state_0\ SETUP 3.510
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_5269/q P6_7(0)_PAD 27.945
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(0,3) 1 Net_5269 Net_5269/clock_0 Net_5269/q 1.250
Route 1 Net_5269 Net_5269/q Net_3983/main_1 2.314
macrocell1 U(1,3) 1 Net_3983 Net_3983/main_1 Net_3983/q 3.350
Route 1 Net_3983 Net_3983/q P6_7(0)/pin_input 6.427
iocell2 P6[7] 1 P6_7(0) P6_7(0)/pin_input P6_7(0)/pad_out 14.604
Route 1 P6_7(0)_PAD P6_7(0)/pad_out P6_7(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
\Control_Reg_1:Sync:ctrl_reg\/control_0 P6_7(0)_PAD 28.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,3) 1 \Control_Reg_1:Sync:ctrl_reg\ \Control_Reg_1:Sync:ctrl_reg\/busclk \Control_Reg_1:Sync:ctrl_reg\/control_0 2.050
Route 1 Net_5057 \Control_Reg_1:Sync:ctrl_reg\/control_0 Net_3983/main_0 2.332
macrocell1 U(1,3) 1 Net_3983 Net_3983/main_0 Net_3983/q 3.350
Route 1 Net_3983 Net_3983/q P6_7(0)/pin_input 6.427
iocell2 P6[7] 1 P6_7(0) P6_7(0)/pin_input P6_7(0)/pad_out 14.604
Route 1 P6_7(0)_PAD P6_7(0)/pad_out P6_7(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 29.076
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,4) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_5411/main_0 3.207
macrocell2 U(0,5) 1 Net_5411 Net_5411/main_0 Net_5411/q 3.350
Route 1 Net_5411 Net_5411/q Tx_1(0)/pin_input 6.355
iocell4 P6[0] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 14.914
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb RTS_1(0)_PAD 26.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,5) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 Net_5517 \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb RTS_1(0)/pin_input 7.423
iocell6 P15[5] 1 RTS_1(0) RTS_1(0)/pin_input RTS_1(0)/pad_out 15.925
Route 1 RTS_1(0)_PAD RTS_1(0)/pad_out RTS_1(0)_PAD 0.000
Clock Clock path delay 0.000